CPE/EE 422/522, Laboratory Assignment 1

Seven Segment Hexadecimal Converter

Summer Semester 2003

 (10% of Final Grade)

Purpose

The purpose of this laboratory is to illustrate how a combinational design can be created using traditional digital design techniques. Students will then be introduced to the internals of the design compilation process when they implement by hand their designs on two programmable logic devices, PLDs (a reprogrammable ROM type device and a PAL). These implementations will be compared to that automatically made by the Altera CAD tool on a much larger PLD.

The Design Problem

In this three-part laboratory, students will be required to implement the simple display converter circuit which is shown in Figure 1 using three different programmable logic devices. This display converter circuit is to contain the logic necessary to drive each segment of the seven segment display in a manner in which the symbol associated with the four bit input is displayed. The symbol pattern that is displayed depends upon the actual four bit code that is being implemented. The most common example would be to display a symbol associated with the 8-4-2-1 weighted binary value that is associated with the four input lines. Thus the symbol 0 would be displayed if all of the input bits were logic low, and the symbol 8 would be displayed if bit I3 was high and the rest low. This is an example of the standard 8-4-2-1 weighted code, but others are possible and may be useful in certain situations. Tables 1- 6 illustrate six possible four bit codes that could be implemented and displayed on a seven-segment display.

 

Standard Binary 8-4-2-1 Weighted Code

  Inputs

  Display

  Configuration

  Inputs

  Display

  Configuration

  I3

  I2

  I1

  I0

  I3

I2

I1

I0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

1

0

0

1

0

 

0

1

0

0

0

1

1

1

0

1

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

0

1

1

0

1

1

1

0

0

1

1

1

1

1

1

1

 

Complemented Input 8-4-2-1 Weighted Binary Code

Inputs

Display

Configuration

Inputs

Display

Configuration

I3

I2

I1

I0

I3

I2

I1

I0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

1

0

0

1

0

1

0

1

0

0

0

1

1

1

0

1

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

0

1

1

0

1

1

1

0

0

1

1

1

1

1

1

1

 

Binary Coded Decimal (BCD)

Inputs

Display

Configuration

Inputs

Display

Configuration

I3

I2

I1

I0

I3

I2

I1

I0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

1

0

0

1

0

1

0

1

0

0

0

1

1

1

0

1

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

0

1

1

0

1

1

1

0

0

1

1

1

1

1

1

1

 

Complemented Input Binary Coded Decimal (BCD)

Inputs

Display

Configuration

Inputs

Display

Configuration

I3

I2

I1

I0

I3

I2

I1

I0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

1

0

0

1

0

1

0

1

0

0

0

1

1

1

0

1

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

0

1

1

0

1

1

1

0

0

1

1

1

1

1

1

1

 

Gray Code

Inputs

Display

Configuration

Inputs

Display

Configuration

I3

I2

I1

I0

I3

I2

I1

I0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

1

0

0

1

0

1

0

1

0

0

0

1

1

1

0

1

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

0

1

1

0

1

1

1

0

0

1

1

1

1

1

1

1

 

Excess-3 Code

Inputs

Display

Configuration

Inputs

Display

Configuration

I3

I2

I1

I0

I3

I2

I1

I0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

0

1

0

0

1

0

1

0

1

0

0

0

1

1

1

0

1

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

  0

1

1

0

1

1

1

0

  0

1

1

1

1

1

1

1

Part 1 -- EPROM Implementation

In the first part of this laboratory experiment students are asked to implement one (1) of the codes listed in the previous tables (Table 1 -- Table 6) using a nonvolatile ROM-type device, a 27C256 EPROM. Your Laboratory instructor will assign you the particular code you are to implement at the time you enter the lab. This will be used for all three parts of the experiment.

Background Information

EPROM

The pinouts for the 27C256 device that will be used in this experiment is shown in Figure 2 below:

In addition to the Vcc and gnd pins (which should be driven at TTL voltage levels of 5V and 0V respectively), there are eight data lines labeled D0 -- D7, and fifteen address lines labeled A0 -- A14. There are also the special pins Vpp, /CE/pgm, and /OE. Vpp is used to supply the higher than TTL level constant voltage needed to program the device. After the device is programmed it needs to be placed at the same voltage as Vcc which is 5V. The /CE/pgm (chip enable/program) pin has a dual purpose. In programming mode it is pulsed at the appropriate voltage in the manner defined by the manufacture. In normal mode, a logic high will disable the chip meaning that the chip will not respond to the address pin inputs and all eight output pins will be tri-stated. If a logic low, is placed on the /CE/pgm input the chip will respond to the address lines -- the results of which will be evident after the propagation delay that is associated with the EPROM (which is in the order of hundreds of nS). The output will not drive the data lines however unless the /OE (output enable) line is driven to a logic low.Like more modern FLASH and EEPROM memory this EPROM's ROM table can be reprogrammed thousands of times, but it must be removed from the circuit and it must be exposed to ultra violet light for several minutes (20-30 for the EPROM eraser used in the lab) to erase its contents so it can be reprogrammed.

Seven Segment LEDs

A single seven-segment indicator can be used to display the digits `0' through `9' and the hexadecimal symbols `A' through `F' (with symbols `b', and `d' being displayed in lower case format) by lighting up the appropriate set of segments. For example, the number `8' can be displayed by illuminating all seven segments and the lower case letter `b' can be displayed by illuminating the segments labeled c,d,e,f, and g for the seven segment display element that is shown in Figure 1.1.:

One common type of seven segment display unit utilizes Light Emitting Diodes, LEDs, as the display elements. In this arrangement, each segment that makes up the seven segment display unit is a separate LED that will light up when it is forward biased1. Often commercially available seven-segment LED display units minimize the number of external pins needed by internally connecting together one node of each of the seven individual LEDs. In one arrangement, the common anode configuration, the anodes of the segment diodes are all connected together in the other arrangement, common cathode , the cathodes of the diodes have a common connection point. If the common point of a common anode seven segment LED is connected to VCC (5 Volts in standard TTL logic) and a set of current limiting resistors are connected in series with the individual segments, as shown in Figure 3, then each segment of the display can be independently illuminated by placing a logic low on the corresponding segment lead (assuming the logic device is capable of sinking enough current to light the LED). In a similar manner if the common point of a common cathode seven segment LED is connected to ground and a set of current limiting resistors are connected in series with the individual segments (see the Note in Figure 4) then each segment of the display can be independently illuminated by placing a logic high on the corresponding segment lead (assuming the logic device is capable of sourcing enough current).

In the first two parts of this experiment it is assumed that a common anode seven segment LED will be used as the targeted display element with the common anode point being connected to Vcc. Thus a logic low will be required to light up each segment. In the next laboratory, where a prototype design is to be actually implemented, a common cathode LED will be used (the reason for this design change will be described later) so a basic overview of both types of seven segment LEDs has been presented.

Entering ROM Table Data in the EPROM

In this part of the lab students will use a simple text editor program such as notepad to enter and edit their ROM tables. To aid the students in the process a template file called Rom.txt, is present on their desktop. Students are to copy this file onto their X: (network) drive and place it right under the root Folder (i.e. X:\Rom.txt). Once they have done this they can make the necessary changes to this program to reflect their desired ROM table. In this file any line that starts with the # character and any lines that are blank are ignored. Rom table data is expressed simply by placing the address on the same line as the corresponding data. The address is expressed in decimal and the data is expressed in binary.

Since the files are so small a 3 1/2 diskette will be used to transport the binary version of the file over to the EPROM programmer. To make this file, simply save all changes that were made in the X:\Rom.txt file, place a floppy in the floppy drive of the computer you are working on, and click on the Rom Transfer icon. This will convert and copy your ROM table information that you specified into a file that is called rom.bin on the floppy. If there are basic format problems then error messages will appear and all memory locations which are not specified will be set to the value 11111111.

After the Rom.bin file has been made on the floppy then this file should be loaded into the PLD programmer. First take the 3 1/2 floppy diskette and a blank 27C256 EPROM over to one of the three available PLD programmers in the lab. The instructions to program the 27C256 EPROM will be presented in the lab.

 Part 1: Assignment

Your laboratory instructor will assign you a particular code from Tables 1-6 which you are to implement in all three portions of the laboratory assignment. Assume the EPROM will be connected in a manner that the Address lines A4--A14 are grounded, and address lines A0--A3 are connected to the switches. Also assume Data line D6 is connected to segment g of the LED, Data line D5 is connected to segment f, Data line D4 is connected to segment e, etc. until data line D0 is connected to segment a of the LED. (Data line D7 is not connected). Assume Vpp is at a logic high and /CE/pgm and /OE are both at a logic low. Develop, implement and demonstrate your design using the TTL digital logic trainers that are in the lab.

Part 2: Logic minimization, Simulation, and Altera Implementation

In this part of this laboratory students will be required to derive the minimized two level Sum-of-Products Expression (SOP) AND/OR logic that is needed to implement a display converter for the assigned code from the previous tables that was implemented in Part I. Students are to perform this minimization before entering the laboratory using standard Karnaugh Map techniques.The four inputs to the display converter network (I3, I2, I1, I0,) shown in each of the previous tables represent a particular type of binary code which can be displayed by the seven segment display. Each student is to implement a display converter circuit for the code that was assigned in part one of this laboratory. Student's are to again assume that a logic low ("0") is needed to light up a segment and a logic high ("1") will turn off the segment. To do this students must complete the following tasks before coming to the lab.

a) create seven separate truth tables one for each segment of the seven segment LED. Each truth table should have the same four inputs (I3, I2, I1, I0) and one output (O6, O5, O4, O3, O2, O1, or O0 as defined by the system level connection pattern shown in Figure 1.3). The truth tables should describe the desired Boolean behavior needed to implement the assigned binary code.

b) convert each truth table into a Karnaugh map then derive the minimum Sum-of-Products Expression (SOP) for each output. Present the resulting seven Boolean equations to your lab instructor before implementing them using the Altera MAX+plus II design package. Using schematic capture, each student is to enter the design that corresponds to the set of minimized equations that was developed in the prelab assignment by using the prim library elements that are present within the Altera MAX+plus II design package. Students are allowed to use multiple input AND gates, OR gates and inverters. Students should first simulate their designs within the Altera MAX+plus II environment using an exhaustive set of test vectors (i.e. the inputs should take on all sixteen possible values) then they should actually implement the design on the Altera UP-1 Educational Board.Part 3: PAL Implementation

In this part of this laboratory, students will be required to utilize a small combinational PAL to implement a display converter logic for the assigned code from the previous tables that was implemented in Parts I and II of this laboratory. Students will be asked to make use of their two level minimized logic equations that they developed in Part II of this experiment to determine how to configure the fuse data in the 16L8 PAL.To aid the debugging processes, the PAL must be connected to the external switches and segments of the LED in the manner shown in Figure 5 below:

Figure 6 shows the logic diagram for the 16L8 PAL. Students will be given an enlarged copy of this diagram to aid them in manually configuring the device to implement the desired function.

Part 3: Assignment

Students are to develop, implement and demonstrate their design using a single 16L8 compatible PAL (or GAL) and a seven segment common cathode LEDs on the TTL digital logic trainers that are in the lab.

Entering Fuse Table Data in the EPROM

In this part of the lab students will use a simple text editor program such as notepad to enter and edit their Fuse data tables. To aid the students in the process a template file called Pal.txt, is present on their PC desktop. Students are to copy this file onto their X: (network) drive and place it right under the root Folder (i.e. X:\Pal.txt). Once they have done this they can make the necessary changes to this program to reflect their desired Fuse Table data. Figure 7 illustrates the basic format of this file and how it relates to the fuse information present within the PAL.

 

A portion of an example Pal.txt file for the display converter design is shown in Figure 7, along with the part of the corresponding logic diagram for the 16L8 PAL that shows the fuse connection points. This file conforms to one of the Joint Electronic Device Engineering Council's (JEDEC) standards. The fuse data in this file is shown to help illustrate the basic JEDEC format and does not necessarily correspond to any actual configuration that is to be produced in the lab. The major portion of this file contains the fuse data, which is set up in a 64 row X 32 column array, with each entry corresponding to a specific connection point in the actual 16L8 fuse array as shown in Figure 7. A 16L8 PAL is manufactured will all fuses present. During the programming process the JEDEC file is parsed by the programming software and when the fuse data for a specified fuse location is "1," the corresponding fuse is blown (i.e. removed) and when it is "0" the fuse is left intact.The lower part of Figure 7 shows the configuration of a 16L8 PAL that results from the first eight rows of fuse data in the JEDEC file. From this file, it is obvious that all of the fuses in the first row are to be removed by the programming process. In the actual device when this happens an internal "pull up" mechanism will cause the output of the corresponding AND gate to have a logic value of "1". Since the fuses in first row of the example have all been removed this will enable the tri-state inverting buffer which now will simply act as an inverter that will drive the corresponding output pin with the complement of the value supplied to it by the seven-input OR gate. The other seven rows correspond to fuse elements that feed the common OR gate. The three bottom lines all have values of logic "0", which means that all of the fuses are left intact. This means that the outputs associated with the AND gates that feed the common OR gate will be logic "0" since both the true and complemented forms of each input enter the AND gates. The four remaining rows in the JEDEC file result in contributing product terms that enter the OR gate that is associated with the O(6) output as shown in Figure 3. The fuse pattern results in the Boolean expression being implemented by the PAL.

[Note: as you implement the actual design one should note that the 16L8 contains an inverting tri-state buffer. This means that if the actual equations from Part II of this experiment were implemented within the AND/OR arrays of the PAL then the output would be the complement of what was desired. To counter this we are using a common cathode LED which in effect cancels out the inversion property of the tri-state inverter. In other words, in this implementation we are using common cathode LEDs where a logic high is required to light up each segment. Your original equations were designed assuming a logic low will light up the LED so your reduced equations from Part II should correspond to the logic that is present before the tri-state inverter. In Parts I and II we used a common anode LED. Switching to a common cathode LED allowed us to counter the effect of the inverter and use the same equations that we derived in Part I.]

The template file Pal.txt is a JEDEC formatted file which contains all of the 16L8 functional fuse information with the initial configuration being that all 2048 fuses will be present. The student is to modify this information by closely examining the equations and then modifying their copy of the Pal.txt file on their X: drive so as to cause the programmer to "blow" the necessary fuses. The student will then invoke a special Pal transfer program to copy this information to the floppy drive, in a similar manner as they invoked the rom transfer program in Part I of this laboratory. Since the file is so small a 3 1/2 diskette will be used to transport the binary version of the file over to the PAL programmer. To make this file, simply save all changes that were made in the X:\Pal.txt file, place a floppy in the floppy drive of the computer you are working on, and click on the Pal Transfer icon. This will convert and copy your PAL fuse map information in the Pal.txt file you specified into a file that is called Pal.jed on the floppy. True 16L8 PALs are one time programmable, OTP, devices. This means that every time a new configuration is needed a new device must be configured. To overcome this problem, we are actually using 16V8 GALS which can be placed in a mode that is compatible with the 16L8 PAL but unlike the 16L8 PAL can be reconfigured as much as necessary in the field. This file has additional fuses which are used to allow the device to emulate a number of other devices such as the 16L8 PAL. One of the functions of the Pal Transfer program is to automatically append to the information in the Pal.txt file the additional fuse information that allows it emulate the 16L8 PAL.

After the Pal.jed file has been made on the floppy then this file should be loaded into the PLD programmer. First take the 3 1/2 floppy diskette and a 16V8 GAL over to one of the three available PLD programmers in the lab. The instructions to configure the 16V8 GAL to emulate the 16L8 PAL are as follows:

MFR: AMD

TYPE: PALCE16V8H

MFR: SGS-THOMSON

TYPE: GAL16V8A/AS/GAL16AS

MFR: LATTICE

TYPE: GAL16V8A/B/B-7/C/Z

Or some other compatible chip as directed by your laboratory instructor.

After the PAL is programmed place the PAL in the physical configuration shown in Figure 5 and demonstrate the design to the laboratory instructor using one of the TTL digital logic trainers that are in the lab